Voltage Set-up Problem on Embedded Systems with Multiple Voltages

Dynamic voltage scaling (DVS), arguably the most effective energy reduction technique, can be enabled by having multiple voltages physically implemented on the chip and allowing the operating system to decide which voltage to use at run-time. Indeed, this is predicted as the future low-power system by International Technology Roadmap for Semiconductors (ITRS). There still exist many important unsolved problems on how to reduce the system's dynamic and/or total power by DVS. One of such problems, which we refer to as the voltage set-up problem, is "how many levels and at which values should voltages be implemented for the system to achieve the maximum energy saving". It challenges whether DVS technique's full potential in energy saving can be reached on multiple-voltage systems. In this paper, (1) we derive analytical solutions for dual-voltage system. (2) For the general case that does not have analytic solutions, we develop efficient numerical methods that can take the overhead of voltage switch and leakage into account. (3) We demonstrate how to apply the proposed algorithms on system design. (4) Interestingly, the experimental results, on both real life DSP applications and random created applications, suggest that multiple-voltage DVS systems with only a couple levels of voltages, when set up properly, can be very close to DVS technique's full potential in energy saving. Parts of this report were published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 7, pp. 869-872, July 2005

A Combined Gate Replacement and Input Vector Control Approach

Due to the increasing role of leakage power in CMOS circuit's total power dissipation, leakage reduction has attracted a lot of attention recently. Input vector control (IVC) takes advantage of the transistor stack effect to apply the minimum leakage vector (MLV) to the primary inputs of the circuit during the standby mode. However, IVC techniques become less effective for circuits of large logic depth because theMLV at primary inputs has little impact on internal gates at high logic level. In this paper, we propose a technique to overcome this limitation by directly controlling the inputs to the internal gates that are in their worst leakage states. Specifically, we propose a gate replacement technique that replaces such gates by other library gates while maintaining the circuit's correct functionality at the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction, when the MLV is not effective. We then describe a divideand- conquer approach that combines the gate replacement and input vector control techniques. It integrates an algorithm that finds the optimal MLV for tree circuits, a fast gate replacement heuristic, and a genetic algorithm that connects the tree circuits. We have conducted experiments on all the MCNC91 benchmark circuits. The results reveal that 1) the gate replacement technique itself can provide 10% more leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; 3) when we obtain the optimal MLV for small circuits from exhaustive search, the proposed gate replacement alone can still reduce leakage current by 13% while the divide-and-conquer approach reduces 17%

Temperature-Aware Leakage Minimization Techniques for Real-Time Systems

In this paper, we study the interdependencies between system's leakage and on-chip temperature. We show that the temperature variation caused by on-chip heat accumulation has a large impact in estimating the system's leakage energy. More importantly, we propose an online temperature-aware leakage minimization technique to demonstrate how to incorporate the temperature information to reduce energy consumption at real time. The basic idea is to run when the system is cool and the workload is high and to put the system to sleep when it is hot and the workload is light. The online algorithm has low run-time complexity and achieves significant leakage energy saving. In fact, we are able to get about 25% leakage reduction on both real life and artificial benchmarks. Comparing to our optimal offline algorithm, the above online algorithm provides similar energy savings with similar decisions on how to put the system to sleep and how to wake it up. Finally, our temperature-aware leakage minimization techniques can be combined with existing DVS methods to improve the total energy efficiency by further saving on leakage

3-Chloro-N′-(3,5-dibromo-2-hy­droxy­benzyl­idene)benzohydrazide methanol monosolvate

The title Schiff base compound, C14H9Br2ClN2O2·CH3OH, features an intra­molecular O—H⋯N hydrogen bond, which contributes to the planarity of the mol­ecule: the dihedral angle between the two benzene rings is 4.6 (2)°. In the crystal, pairs of adjacent mol­ecules are linked through inter­molecular N—H⋯O and O—H⋯O hydrogen bonds, forming dimers. The methanol solvent mol­ecule is linked by inter­molecular O—H⋯O hydrogen bonds

MES-Attacks: Software-Controlled Covert Channels based on Mutual Exclusion and Synchronization

Multi-process concurrency is effective in improving program efficiency and maximizing CPU utilization. The correct execution of concurrency is ensured by the mutual exclusion and synchronization mechanism (MESM) that manages the shared hardware and software resources. We propose MES-Attacks, a new set of software-controlled covert channel attacks based on MESM to transmit confidential information. MES-Attacks offer several advantages: 1) the covert channels are constructed at software level and can be deployed on any hardware; 2) closed share of resource ensures the quality of the channels with low interference and makes them hard to be detected; and 3) it utilizes the system's software resources which are abound and hence difficult to isolate. We built covert channels using different MESMs on Windows and Linux, including Event, Timer, FileLockEX, Mutex, Semaphore and flock. Experimental results demonstrate that these covert channels can achieve transmission rate of 13.105 kb/s, 12.383 kb/s, and 6.552 kb/s, respectively in the scenarios of local, cross-sandbox and cross-VM, where the bit error rates are all under 1\%

Publicly Detectable Watermarking for Intellectual Property Authentication in VLSI Design

Highlighted with the newly released intellectual property (IP) protection white paper by VSI Alliance, the protection of virtual components or IPs in very large scale integration (VLSI) design has received a great deal of attention recently. Digital signature/watermark is one of the most promising solutions among the known protection mechanisms. It provides desirable proof of authorship without rendering the IP useless. However, it makes the watermark detection, which is as important as watermarking, an NP-hard problem. In fact, the tradeoff between hard-to-attack and easy-to-detect and the lack of efficient detection schemes are the major obstacles for digital signatures to thrive. In this paper, the authors propose a new watermarking method which allows the watermark to be publicly detected without losing its strength and security. The basic idea is to create a cryptographically strong pseudo-random watermark, embed it into the original problem as a special (which the authors call mutual exclusive) constraint, and make it public. The authors combine data integrity technique and the unique characteristics in the design of VLSI IPs such that adversaries will not gain any advantage from the public watermarking for forgery. This new technique is compatible with the existing constraint-based watermarking/fingerprinting techniques. The resulting public–private watermark maintains the strength of a watermark and provides easy detectability with little design overhead. The authors build the mathematical framework for this approach based on the concept of mutual exclusive constraints. They use popular VLSI CAD problems, namely technology mapping, partitioning, graph coloring, FPGA design, and Boolean satisfiability, to demonstrate the public watermark’s easy detectability, high credibility, low design overhead, and robustness